Possible enhancement: add AWCACHE parameter to axis2mm
baileyji opened this issue · comments
In exploring design options for our larger system I've discovered that xilinx's documentation for their AXI data width converter will only pack bursts when upsizing if AWCACHE[1] (I think) is set. Presently I've simply hardcoded b0011 to test (and I think I see how to add it to the verilog with a pull request. As my HDL is extremely limited I thought instead I'd call your attention to this as a potential enhancement that might help with downstream throughput.
AxCACHE is supposed to be set to 4'h3 in all my designs. It looks like you found one I missed.
Dan
Should be fixed now.