ZipCPU / wb2axip

Bus bridges and other odds and ends

axi2axilite missing DW on axi_addr instances

saberhawk opened this issue 4 years ago · comments

saberhawk commented 4 years ago

The axi2axilite module is missing DW on both axi_addr instances which can cause incorrect addressing when C_AXI_DATA_WIDTH is set to 64

wb2axip/rtl/axi2axilite.v

Line 283 in 3d7374e

axi_addr #(.AW(C_AXI_ADDR_WIDTH))

Dan Gisselquist commented 4 years ago

Thanks!

Fixed in 69b849d.

Dan