YiminGao0113

pypuf

Cryptanalysis of Physically Unclonable Functions

puffery

Tools for PUF analysis

design-resources

A collection of Opal Kelly provided design resources

RISC-V-Vector-Processor

256-bit vector processor based on the RISC-V vector (V) extension

Super_SPI_Master_Verilog

SPI Master Verilog module

SPI

Verilog 2001 implementation of part of Microchip's 23A640 SPI Bus low-power serial SRAM.

spi_mem_programmer

Small (Q)SPI flash memory programmer in Verilog

verilog_spi

A simple Verilog SPI master / slave implementation featuring all 4 modes.

riscv-tests

twitchcore

It's a core. Made on Twitch.

serv_soc

SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.

FirefoxCSS

Custom firefox interface

migen

A Python toolbox for building complex digital hardware

SpinalHDL

Scala based HDL

convolution-flavors

Implementation of convolution layer in different flavors

black-parrot

A Linux-capable RISC-V multicore for and by the world

serv

SERV - The SErial RISC-V CPU

minerva

A 32-bit RISC-V soft processor

PiMulator

Processing in Memory Emulation

Cache-Controller

Two Level Cache Controller implementation in Verilog HDL

iob-cache

Verilog Configurable Cache

mindspore

MindSpore is a new open source deep learning training/inference framework that could be used for mobile, edge and cloud scenarios.

linux-on-litex-blackparrot

Linux on Litex for BlackParrot Core

litex

Build your hardware, easily!

Cores-VeeR-EH1

VeeR EH1 core

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Direct-Mapped-Cache

Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

MNIST-CNN-99.5

litex-vexriscv-tensorflow-lite-demo

TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board