UmerShahidengr

rocket-chip

Rocket Chip Generator

verilator

Verilator open-source SystemVerilog simulator and lint system

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

riscv-opcodes

RISC-V Opcodes

black-parrot

A Linux-capable RISC-V multicore for and by the world

sail

Sail architecture definition language

Computer-Science-Textbooks

Collect some CS textbooks for learning.

riscv-pk

RISC-V Proxy Kernel

riscv-arch-test

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-code-size-reduction

riscv-toolchain-conventions

Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains

cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P

riscv-profiles

RISC-V Architecture Profiles

pulp_soc

pulp_soc is the core building component of PULP based SoCs

riscv-config

RISC-V Configuration Validator

riscv-ctg

riscv-isac

ai_on_chip_project1

tpu-systolic-array-weight-stationary

Rev-Soc

ubuntu_beaglev

Ubuntu on BeagleV

Vivado-Installation

riscv-validation

Scripts/tests/configurations needed for configuring a real RISC-V board in gem5 live here