Problem on multi-master

[Anderson Ignacio]

Hi @rherveille and @sphardy ,
I'm using the interconnect to integrate 2x AHB memories as slaves and 2x masters that represents the interfaces of a CPU (I/D Bus). So, the problem that I'm facing right now that in some requests from the masters with conflicts, where it overlap the addresses (both I/D buses are requesting on the same range), the slave does not receive the requests as it should.

In the image above, you can see that both interfaces are requesting on the same range and in the memory perspective, the two requests are not achieving the slave. Also, in another moments like the image below, both requests are answered with the correct signals been driven by the interconnect.

Ps.: the memory address of IRAM it's 0xAA0000 with 16k of range

[rherveille]

Hi, Can you provide a testbench that highlights the problem? Thanks, Richard

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Sent from my iPhone On 15 Jul 2019, at 20:25, Ânderson Ignacio da Silva <[e-mail]<mailto:[e-mail]>> wrote: Hi @rherveille<https://github.com/rherveille> and @sphardy<https://github.com/sphardy> , I'm using the interconnect to integrate 2x AHB memories<https://roalogic.github.io/ahb3lite_memory/DATASHEET.html> as slaves and 2x masters that represents the interfaces of a CPU (I/D Bus). So, the problem that I'm facing right now that in some requests from the masters with conflicts, where it overlap the addresses (both I/D buses are requesting on the same range), the slave does not receive the requests as it should. [Screenshot from 2019-07-15 20-19-33]<https://user-images.githubusercontent.com/5991372/61238916-f7939a00-a73d-11e9-9bbf-9feee59c2224.png> In the image above, you can see that both interfaces are requesting on the same range and in the memory perspective, the two requests are not achieving the slave. Also, in another moments like the image below, both requests are answered with the correct signals been driven by the interconnect. [Screenshot from 2019-07-15 20-20-07]<https://user-images.githubusercontent.com/5991372/61239053-4f320580-a73e-11e9-8e57-5c9abed55d4d.png> Ps.: the memory address of IRAM it's 0xAA0000 with 16k of range — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub<#3?email_source=notifications&email_token=ADYKSCP4F7MNJOCNLW3X4FDP7S6H7A5CNFSM4IDZQM7KYY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4G7JHS7Q>, or mute the thread<https://github.com/notifications/unsubscribe-auth/ADYKSCLV6KS4IMKY5R4I7YDP7S6H7ANCNFSM4IDZQM7A>.

[Anderson Ignacio]

Hi @rherveille
thanks for the answer. Please check the files attached on the .zip.
tb_ahb.zip

[rherveille]

Thanks for the quick response. I am out for a few days, when I am back in the office I will take a look. Richard

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Sent from my iPhone On 16 Jul 2019, at 11:58, Ânderson Ignacio da Silva <[e-mail]<mailto:[e-mail]>> wrote: Hi @rherveille<https://github.com/rherveille> thanks for the answer. Please check the files attached on the .zip. tb_ahb.zip<https://github.com/RoaLogic/ahb3lite_interconnect/files/3396552/tb_ahb.zip> — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub<#3?email_source=notifications&email_token=ADYKSCLF2646CM3YIFBNX73P7WLVPA5CNFSM4IDZQM7KYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOD2ALGDA#issuecomment-511750924>, or mute the thread<https://github.com/notifications/unsubscribe-auth/ADYKSCOBJ7WACFCTKAMUMZTP7WLVPANCNFSM4IDZQM7A>.

[Anderson Ignacio]

Thanks @rherveille , also I have some other issues related to the other repo (ahb3lite-memory) some "X"s that appeared on the simulation and I should set some .re_i input in the generic memory instantiation to avoid that conditions...

[rherveille]

This has been fixed. This was a user issue due to incorrect HREADY and HREADYOUT connections