drichmond

RISC-V-On-PYNQ

RISC-V Integration for PYNQ

PYNQ-HLS

A Tutorial on Putting High-Level Synthesis cores in PYNQ

HOPS

Synthesizable Higher-Order Functions (Patterns) for C++

PYNQ-Hackathon-2017

General Repository for PYNQ Hackathon Resources

Python-Arduino-Command-API

A Python library for communicating with Arduino microcontroller boards

riffa-development

The RIFFA development repository

Challenge-II

PYNQ Hackathon 2017 Challenge 2

PYNQ

Python Productivity for ZYNQ

pynq-copter

PYNQ-Networking

Networking Overlay on PYNQ

PYNQ-ZeroTier-Instructions

A short tutorial on how to install ZeroTier on PYNQ (2.3+)

RV12

RISC-V CPU Core

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

DRAMsim3

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

orca

RISC-V by VectorBlox

readthedocs.org

source code to readthedocs.org

riscv-tests

rocket-chip

Rocket Chip Generator

verilator

Verilator open-source SystemVerilog simulator and lint system

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

wireshark

Read-only mirror of Wireshark's Git repository. GitHub won't let us disable pull requests. ☞ THEY WILL BE IGNORED HERE ☜ Please upload them at https://code.wireshark.org/review/ .

blog_yosyshq

Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

pytest_utils

Package for producing Gradescope-compatible results.json files with Pytest tests

sampa-public

the Sampa group website

ShEF

Shielded Enclaves for Cloud FPGAs