Florent's starred repositories

hdl

HDL libraries and projects

Language:VerilogLicense:NOASSERTIONStargazers:1415Issues:160Issues:79

edalize

An abstraction library for interfacing EDA tools

Language:PythonLicense:BSD-2-ClauseStargazers:603Issues:34Issues:157

PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Language:VHDLLicense:NOASSERTIONStargazers:529Issues:58Issues:54

libiio

A cross platform library for interfacing with local and remote Linux IIO devices

Language:CLicense:LGPL-2.1Stargazers:471Issues:56Issues:367

UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

Language:VHDLLicense:Apache-2.0Stargazers:342Issues:54Issues:186

fpga_readings

Recipe for FPGA cooking

Language:VerilogLicense:Apache-2.0Stargazers:276Issues:29Issues:4

display_controller

FPGA display controller with support for VGA, DVI, and HDMI.

Language:VerilogLicense:MITStargazers:202Issues:17Issues:2

vhdl-style-guide

Style guide enforcement for VHDL

Language:PythonLicense:GPL-3.0Stargazers:176Issues:11Issues:829

cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

Language:PythonLicense:BSD-2-ClauseStargazers:101Issues:13Issues:60

SpaceWireToGigabitEther

Open-source version of SpaceWire-to-GigabitEther using ZestET1

zynq-ultrascale-readback-capture

This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the same task to Zynq UltraScale+ MPSoC with several noticeable differences.

Language:TclStargazers:13Issues:3Issues:0

FREtZ

FPGA Reliability Evaluation through JTAG

Language:TclLicense:GPL-3.0Stargazers:8Issues:2Issues:1