Florent's repositories
core_dbg_bridge
UART -> AXI Bridge
Language:VerilogLGPL-2.1000
drawio-github
Drawio GitHub Integration
Language:HTML000
LiberoSoC-Docker
Docker image for running LiberoSoC
Language:Dockerfile000
neorv32
A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Language:VHDLBSD-3-Clause000
neorv32-riscof
✔️Port of RISCOF to verify the NEORV32 Processor's RISC-V ISA compatibility.
Language:PythonBSD-3-Clause000
rfid-mp3
Arduino-controlled kids' audio player
Language:C++MIT000
SpaceWireToGigabitEther
Open-source version of SpaceWire-to-GigabitEther using ZestET1
Language:Python000
vhdl-hdmi-out
HDMI Out VHDL code for 7-series Xilinx FPGAs
Language:VHDLGPL-3.0000