LeFl0w / neorv32-riscof

✔️Port of RISCOF to verify the NEORV32 Processor's RISC-V ISA compatibility.

NEORV32 Core Verification using RISCOF

1. Prerequisites
2. Setup Configuration
3. Device-Under-Test (DUT)

This repository is a port of the "RISCOF RISC-V Architectural Test Framework" to test the NEORV32 RISC-V Processor for compatibility to the RISC-V user and privileged ISA specifications. Sail RISC-V is used as reference model. Currently, the following tests are supported:

• rv32i_m\B - bit-manipulation (Zba, Zbb, Zbc, Zbs)
• rv32i_m\C - compressed instructions
• rv32i_m\I - base integer ISA
• rv32i_m\M - hardware multiplication and division
• rv32i_m\privilege - privileged machine architecture
• rv32i_m\Zifencei - instruction stream synchronization

💡 The general structure of this repository was setup according to the RISCOF installation guide.

Prerequisites

Several tools and submodules are required to run this port of the architecture test framework. The repository's GitHub Actions workflow takes care of installing all the required packages.

• neorv32 submodule - the device under test (DUT)
• riscv-arch-test submodule - architecture test cases
• RISC-V GCC toolchain - for compiling native rv32 code
• Sail RISC-V - the reference model (pre-built binary in thebin folder)
• RISCOF - the architecture test framework
• GHDL with coverage support - the awesome VHDL simulator for simulating the DUT

The framework (running all tests) is invoked via a single shell script run.sh that returns 0 if all tests were executed successfully or 1 if there were any errors. The exit code of this script is used to determine the overall success of the GitHub Actions workflow.

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Setup Configuration

The RISCOF config.ini is used to configure the plugins to be used: the device-under-test ("DUT") and the reference model ("REF"). The ISA, debug and platform specifications, which define target-specific configurations like available ISA extensions, ISA spec. versions and platform modules (like MTIME), are defined by YAML files in the according plugin folder.

• DUT: neorv32 in plugin-neorv32
• REF: sail_cSim in plugin-sail_cSim

Each plugin folder also provides low-level environment files like linker scripts (to generate an executable matching the target's memory layout) and platform-specific code (for example to initialize the target and to dump the final test signatures/results).

The official RISC-V architecture tests repository provides test cases for all (ratified) RISC-V ISA extensions (user and privilege ISA). Each test case checks a single instruction or core feature and is compiled into a plugin-specific executable using a prebuilt RISC-V GCC toolchain.

The "golden" reference data is generated by the Sail RISC-V Model. This data is compared against the results of the DUT. The final test report is made available as CSS-flavored HTML file via the GitHib actions artifact.

💡 Prebuilt sail-riscv binaries for 64-bit Linux are available in the bin folder.

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Device-Under-Test (DUT)

The sim folder provides a simple VHDL testbench and shell scripts to simulate the NEORV32 processor using GHDL. The testbench provides generics to configure the DUT's RISC-V ISA extensions and also to pass a plain ASCII HEX file, which represents the actual executable to be executed ("memory initialization file"). This file generated from a test-specific ELF file that is compiled by the folder's makefile. The makefile uses the default software framework from the NEORV32 submodule (more specific: the image generator) to generate a memory initialization file from a compiled ELF file.

The testbench implements four CPU-external memory modules that get initialized with the actual executable. Each memory module implements a_physical memory size of 512kB resulting in a total memory size of 2MB (the largest test case executable comes from the I/jal test case with approx. 1.7MB). This "splitting" is required as GHDL has problems handling large objects (see ghdl/ghdl#1592). The memories are attached to the processor via its external Wishbone bus interface and are mapped to the core's reset address at 0x00000000.

📚 The "simulation mode" feature of the processor's UART0 module is used to dump the test result data (= the test signature) to a file. More information regarding the UART simulation mode can be found in the NEORV32 online documentation.

The testbench also provides a "trigger mechanism" to quit the current simulation using VHDL08's finish statement. Quitting the simulation is triggered by writing 0xCAFECAFE to address 0xF0000000, which is implemented (software) by the DUT-specific plugin environment module.

The simulation scripts and the makefile for generating the memory initialization file are invoked from a DUT- specific Python script in the DUT's plugin folder (-> plugin-neorv32/riscof_neorv32.py). This Python script makes extensive use of shell commands to move and execute files and scripts.

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coverage

GHDL coverage support

GHDL can support coverage with the help of GCC backend with gcov. To enable this feature you have to recompile GHDL with the official procedure or applie the one below if you are running Ubuntu 22.04.1 LTS (change gcc version to yours if not). The new ghdl application will be installed in /opt/ghdl. Do not forget to add it to the path with command export PATH=/opt/ghdl/bin:$PATH to replace your previous ghdl version by this one for the test.

$ sudo apt-get install gnat build-essential libmpc-dev flex bison libz-dev lcov gcc-11-source texinfo gcovr
$ git clone https://github.com/ghdl/ghdl.git
$ cd /usr/src/gcc-11
$ sudo tar xvf gcc-11.3.0.tar.xz 
$ cd gcc-11.3.0
$ ./contrib/download_prerequisites 
$ cd ghdl 
$ mdir build
$ cd build
$ ../configure --with-gcc=/usr/src/gcc-11/gcc-11.3.0 --prefix=/opt/ghdl
$ make copy-sources
$ mkdir gcc-objs; cd gcc-objs
$ /usr/src/gcc-11/gcc-11.3.0/configure  --prefix=/opt/ghdl --enable-languages=c,vhdl --disable-bootstrap --disable-lto --disable-multilib --disable-libssp --disable-libgomp --disable-libquadmath --enable-default-pie
$ make -j4 && make install MAKEINFO=true
$ cd ..
$ make ghdllib
$ make install

collecting coverage report for riscof

The following files have been changed:

• ghdl_run.sh and ghdl_setup.sh to include coverage support during ghdl call.
• riscof_neorv32.py to backcup coverage result in a dedicated coverage folder.

Execute run.sh

acknowledgment

This test was adapted thanks to https://github.com/huettern/ghdl-coverage repository. You can use it to check your ghdl with coverage installation works.