JungleEngine / Project_ARCH_2

Simplified implementation of MIPS pipelined processor

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Introduction

  • This is an implementation of a simplified 5 stage pipepeline microprocesser.
  • Fetch - Decode - Execute - Memory - Write back

About

Simplified implementation of MIPS pipelined processor

License:MIT License


Languages

Language:VHDL 92.1%Language:Stata 7.9%