This repository contains the final report of my ADVD final assignment, wherein I designed 4 input PSUEDO NMOS NOR logic for 180nm SCL technology.
The working schematic is as shown below :
Simulation projects on VLSI design.
This repository contains the final report of my ADVD final assignment, wherein I designed 4 input PSUEDO NMOS NOR logic for 180nm SCL technology.
The working schematic is as shown below :
Simulation projects on VLSI design.