InvincibleJuggernaut / Synthesis

A collection of digital circuits using Verilog.

Repository from Github https://github.comInvincibleJuggernaut/SynthesisRepository from Github https://github.comInvincibleJuggernaut/Synthesis

Synthesis

Introduction

This is a collection of digital circuits written in Verilog.

About

A collection of digital circuits using Verilog.


Languages

Language:Verilog 85.0%Language:Coq 15.0%