Ikarthikmb

awesome-electronics

A curated list of awesome resources for Electronic Engineers and hobbyists

yosys

Yosys Open SYnthesis Suite

blog-post-workflow

Show your latest blog posts from any sources or StackOverflow activity or Youtube Videos on your GitHub profile/project readme automatically using the RSS feed

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

awesome-mechanical-keyboard

⌨️ A curated list of Open Source Mechanical Keyboard resources.

glasgow

Scots Army Knife for electronics

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

biodiff

Hex diff viewer using alignment algorithms from biology

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

pyuvm

The UVM written in Python

kicad_footprints

A collection of all the KiCad footprints on the internet

GDS3D

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.

pcbre

An integrated printed circuit board reverse engineering toolkit

Booth_Multipliers

Parameterized Booth Multiplier in Verilog 2001

Circuit-Designers-Etiquette

A set of rules and recommendations for analog and digital circuit designers.

avsdpll_1v8_sky130_ss

Hardware-Programming

Codes related with Arduino UNO, NodeMCU, RasbpberryPi, MATLAB.

dvsd_wt8216m

IP layout design of a 8-bit binary multiplier using sky130 pdk with OpenLane

wallace-tree

Design of a CMOS n-bit multiplier using Wallace-tree reduction technique with sky130 pdk and esim.

ai_solar_panel_monitor

AI generated Verilog RTL design for Solar Panel monitor

Circuit-Designs

Schematics and PCB designs implemented in Kicad.

ctb2023-challenges-Ikarthikmb

"Capture the Bug" hackathon workspace includes 3 Level challenges, conducted by NIEILT, Vyoma Systems in the year 2023

eSim-Workspace

Designing circuits and projects with eSim EDA Tool

i2c_ctrl2202

I2C Controller

OpenRAM_Tech

rtl_designs

Design of verilog circuits and verifying them

VerilogClocks

Various methods on generating clock signal in verilog.

VerilogFod

challenges-Ikarthikmb

challenges-Ikarthikmb created by GitHub Classroom