HHHHorrible's repositories
Group_SystemGenerator_Guide
这次搞的是赛灵思家的system generator ，应用已经非常广泛了，现在我们先用来校验一下制度问题
AISystem
AISystem 主要是指AI系统，包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi4_vip
Verification IP for AXI protocol
AXI_FIFO_BFM
AXI4 with a FIFO integrated with VIP
BPSK_ASIC
BPSK demodulator ASIC design with Toshiba 45nm lib in verilog for EE 287 Spring 2013
chinessChess
Cross-platform and online battle platform game based on Qt: Chinese Chess
CommPy
Digital Communication with Python
FPGA_CNN
use fpga to create cnn， then realize some ai production
GZHU-Report-Latex-Version
我自己制作的广州大学Latex报告模板，有毕业设计，课程设计，毕业论文，等等🎈
HHHHorrible.github.io
self blog
jekyllthemes
A directory of the best-looking themes for Jekyll blogs
learn2learn
A PyTorch Library for Meta-learning Research
markdown-weixin
一个在线将 Markdown 转换为微信公众帐号文章格式的工具
MSDNet-PyTorch
MSDNet
PaddleDetection
Object Detection toolkit based on PaddlePaddle. It supports object detection, instance segmentation, multiple object tracking and real-time multi-person keypoint detection.
sata3_host_controller
It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
scihub2pdf
Downloads pdfs via a DOI number, article title or a bibtex file, using the database of libgen(sci-hub) , arxiv
tvip-axi
AMBA AXI VIP
Verilog-Automatic
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
verilog-mersenne
Verilog implementation of Mersenne Twister PRNG