EmanOthman21 / PDP-11

A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

PDP-11

Simulation to pdp-11 microprocessor with modelsim , The design is a micro-programmed based with an average of 9 clock cycles per instruction .

Design

  • Control Word Design Word Design
  • System Design System Design

Instructions

  • ALU Instructions
    • 2-Operand Instructions:
      • MOV,ADD,ADC,SUB,SUBC,AND,OR,XOR,CMP
    • 1-Operand Instructions:
      • INC,DEC,CLR,INV,LSR,ROR,ASR,LSL,ROL
  • Branch Instructions
    • BR,BEQ,BNE,BLO,BLS,BHI,BHS
  • 0-Operand Instructions
    • HLT,RST

Addressing modes

  • Register Direct
  • Register Indirect
  • Auto-Increment
  • Auto-Increment Indirect
  • Auto-Decrement
  • Auto-Decrement Indirect
  • Indexed
  • Indexed-Indirect

Assembler

  • An Assembler in python for converting pdp-11 assembly syntax into a binary file.
  • refer to Assembler for the implemented features and running instructions .

Run

  • Create your project in modelsim.
  • Add all the .vhd files in src to the project.
  • Write your code in any editor then run it with the assembler to get the binary file.
  • start your simulation by running .do file as in c1.do after changing the directory of the c1.mem to the directory of your binary file.

Contributors

  • Bassant Mohamed
  • Eman Othman
  • Menna Mahmoud
  • Nada Abdelmaboud

License

MIT licensed

About

A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.

License:MIT License


Languages

Language:VHDL 44.1%Language:Stata 38.9%Language:Python 17.0%