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AngelTerrones / Basic-verilog-project

Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

Repository from Github https://github.comAngelTerrones/Basic-verilog-projectRepository from Github https://github.comAngelTerrones/Basic-verilog-project

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Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

verilogisemyhdlxflow

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Language:Shell 45.5%Language:Verilog 23.2%Language:Python 18.6%Language:Makefile 12.7%