AngelTerrones

Ángel Terrones's repositories

Algol

A RISC-V CPU (Outdated: using priviledge v1.7)

Language:AssemblyMIT25 40

Antares

A MIPS32 release 1 processor.

Language:Verilog3 30

Altair

A RV32I RISC-V soft processor using nMigen

Language:PythonNOASSERTION2 20

Bellatrix

A RV32I RISC-V soft processor using nMigen

Language:PythonNOASSERTION2 30

V-Algol

V(erilog)-Algol - A RISC-V CPU.

Language:CMIT2 30

Mirfak

A RISC-V RV32IM CPU

Language:VerilogMIT1 20

ubuntu-libero

Language:Shell1 20

XSTOOLs

Utilities for the XESS FPGA Boards.

Language:PythonGPL-3.01 20

dotfiles

Dotfiles for Arch Linux

Language:Vim Script020

GA-render-cuda

GA for replicating an image, using CUDA.

Language:C++020

algol_design

Presentación acerca de los pasos realizados para el diseño de mi procesador ALGOL (RV32IM)

Language:Jupyter Notebook020

angelterrones.github.io

Language:HTML020

AoC2020

Advent of Code 2020

Language:Python020

AoC2021

Advent of Code 2021

Language:Python020

banner-myhdl

Language:Python010

Basic-verilog-project

Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

Language:Shell030

Cronometro-USBBOT

Language:C++020

CV

Language:TeX020

DCRN

Distributed Control of Robotic Networks

Language:Python020

GA-render-circle

Language:C++020

M2GL025-Creative-Board-Notes

Notes from tinkering with Microsemi's IGLOO2 RISC-V development board.

GPL-3.0020

MUSB

A MIPS32 release 1 processor (Do not use)

Language:Verilog03 2

riscv-arch-test

Language:CBSD-3-Clause020

scryfall_download

Language:Python010

TeensyDist

Teensy 3.5/3.6 multistage distortion modeling pedal

Language:CGPL-3.0010

UART-myhdl

Language:Python020

USBBOTS16

Página del USBBOTS16

Language:JavaScript020

Vrep-Tutorial

Codigos ejemplos para usar Vrep con ROS y con la api remota.

Language:C010

wosh-presentation

Language:Verilog010

zephyr

Primary GIT Repository for the Zephyr Project

Language:CApache-2.0010