844562078's starred repositories

proteus

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Language:ScalaLicense:MITStargazers:36Issues:0Issues:0

riscv-newlib

RISC-V port of newlib

Language:CLicense:GPL-2.0Stargazers:96Issues:0Issues:0

openocd

Official OpenOCD Read-Only Mirror (no pull requests)

Language:CLicense:NOASSERTIONStargazers:1532Issues:0Issues:0

riskow

Learning how to make a RISC-V

Language:VerilogLicense:Apache-2.0Stargazers:128Issues:0Issues:0

riscv-steel

Open source RISC-V microcontroller unit for FPGAs written in Verilog

Language:VerilogLicense:MITStargazers:116Issues:0Issues:0

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Language:VerilogLicense:Apache-2.0Stargazers:2548Issues:0Issues:0

risc-v

RISC-VのCPU作った

Language:VerilogStargazers:20Issues:0Issues:0

VLSI

RISC V core implementation using Verilog.

Language:VerilogLicense:BSD-3-ClauseStargazers:23Issues:0Issues:0

riscv_sbc

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

Language:VerilogStargazers:25Issues:0Issues:0

RISCV_Piccolo_v1

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

Language:VerilogLicense:MITStargazers:33Issues:0Issues:0

phoeniX

phoeniX RISC-V Processor

Language:VerilogLicense:GPL-3.0Stargazers:91Issues:0Issues:0

RISC-V

A simple RISC-V CPU written in Verilog.

Language:VerilogStargazers:43Issues:0Issues:0

core_uriscv

Another tiny RISC-V implementation

Language:VerilogLicense:Apache-2.0Stargazers:50Issues:0Issues:0

RISC-V-32I

体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器

Language:VerilogStargazers:60Issues:0Issues:0

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Language:VerilogLicense:Apache-2.0Stargazers:67Issues:0Issues:0

RISC-V-CPU

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

Language:VerilogStargazers:192Issues:0Issues:0

riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Language:VerilogLicense:Apache-2.0Stargazers:593Issues:0Issues:0

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Language:VerilogLicense:ISCStargazers:2832Issues:0Issues:0

riscv

RISC-V CPU Core (RV32IM)

Language:VerilogLicense:BSD-3-ClauseStargazers:1123Issues:0Issues:0

e203_hbirdv2

The Ultra-Low Power RISC-V Core

Language:VerilogLicense:Apache-2.0Stargazers:1126Issues:0Issues:0

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Language:VerilogLicense:BSD-3-ClauseStargazers:1929Issues:0Issues:0

awesome-go

A curated list of awesome Go frameworks, libraries and software

Language:GoLicense:MITStargazers:123554Issues:0Issues:0

emitter

High performance, distributed and low latency publish-subscribe platform.

Language:GoLicense:AGPL-3.0Stargazers:3782Issues:0Issues:0

ninja

a small build system with a focus on speed

Language:C++License:Apache-2.0Stargazers:10717Issues:0Issues:0

delve

Delve is a debugger for the Go programming language.

Language:GoLicense:MITStargazers:22271Issues:0Issues:0

neorv32

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Language:CLicense:BSD-3-ClauseStargazers:1466Issues:0Issues:0

ML305A_ML307A_OpenCPU_Standard_1.4.2.2023062518_release

ML305A_ML307A_OpenCPU_Standard_1.4.2.2023062518_release

Language:C++Stargazers:3Issues:0Issues:0

MQTT-C

A portable MQTT C client for embedded systems and PCs alike.

Language:CLicense:MITStargazers:743Issues:0Issues:0

paho.mqtt.javascript

paho.mqtt.javascript

Language:JavaScriptLicense:NOASSERTIONStargazers:1132Issues:0Issues:0

distributions

NodeSource Node.js Binary Distributions

Language:ShellLicense:MITStargazers:13315Issues:0Issues:0