zeeshanrafique23

mdu

M-extension for RISC-V cores.

RV32I-Logisim

RV32I single cycle simulation on open-source software Logisim.

zeeshanrafique23

My GitHub Profile README. Don't just fork, star it, so others can find it too! 👀

rv-compressed

Compressed instruction decoder (C-extension) for RISC-V Cores.

zeeshanrafique23.github.io

My portfolio.

RV32I-Chisel

This repo contains the files of the RV32I Single-cycle processor in CHISEL.

Buraq-mini

RISC-V 5-stage 32-bit (RV32IM) processor.

Buraq-mini-sv

This repository is the contain systemverilog version of Buraq-mini with a seperate branch for veriloator team.

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

opentitan

OpenTitan: Open source silicon root of trust

serv

SERV - The SErial RISC-V CPU

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

azadi

Deprecated: Azadi is an SoC with 32 bit RISC-V CPU core.

azadi-soc

Azadi after tapeout

Certificates

All those certificates which I had achieved till now.

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

corescore

CoreScore

fpnew

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

open_mpw_precheck

tcl

This repo contains the basic programs and practice code for tcl beginners.

TENNA

TENNA: Tiny Embedded Neural Network Accelerator