yuri-panchul / yrv-plus

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

yrv

This RISC-V implementation is described in the book "Inside An Open-Source Processor" ISBN 978-3-89576-443-1

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

Apache License 2.0

Language:Verilog 90.6%Language:SystemVerilog 4.0%Language:Shell 3.5%Language:Tcl 1.8%Language:Batchfile 0.1%Language:Assembly 0.0%