Ya-Chau Yang's repositories
async_FIFO
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.
cosim_bfm_library
HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
CycloneTCP
Dual IPv4/IPv6 Stack
Git-Tutorials
Git-Tutorials GIT基本使用教ĺ¸:memo:
gvsoc
Pulp virtual platform
ipxact2systemverilog
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
Limago
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
obudpst
OB-UDPST is a client/server utility to do UDP-based IP capacity measurements (see TR-471 for details).
PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
RISC-V-TLM
RISC-V SystemC-TLM simulator
Shunt
SystemVerilog DPI "TCP/IP Shunt" (TCP/IP system verilog socket library)
srdl2sv
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
style-guides
lowRISC Style Guides
svmodule
SystemVerilog & Verilog Module I/O parser and printer
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
xgpon
XG-PON Simulation Module for NS-3