ycyang0508

LimeSDRTest

xilinx_iic_hw_ctrl

async_FIFO

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

eth_vlg

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

OpenFPGA

An Open-source FPGA IP Generator

OpenUSRP

using LimeSDR to simulate USRP B210

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.

awesome-opensource-asic-resources

bt_modem

cosim_bfm_library

HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI

CycloneTCP

Dual IPv4/IPv6 Stack

DPI_socket

gen_amba

AMBA bus generator including AXI, AHB, and APB

Git-Tutorials

Git-Tutorials GIT基本使用教學:memo:

gvsoc

Pulp virtual platform

impacket

Impacket is a collection of Python classes for working with network protocols.

ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

obudpst

OB-UDPST is a client/server utility to do UDP-based IP capacity measurements (see TR-471 for details).

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

PlutoSDR_tone_swep

Rev-Soc

RISC-V-TLM

RISC-V SystemC-TLM simulator

Shunt

SystemVerilog DPI "TCP/IP Shunt" (TCP/IP system verilog socket library)

srdl2sv

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

style-guides

lowRISC Style Guides

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

wirehair

Wirehair : O(N) Fountain Code for Large Data

xgpon

XG-PON Simulation Module for NS-3