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Carsten Wulff (carsten@wulff.no)
I wanted a design I could work on to pipeclean cicsim and test out SkyWater 130 nm Open PDK.
A circuit that is almost always needed on an integrated circuit is a bias current source.
Standard bandgap based PTAT current source on vertical pnp transistors.
See chapter 7.3.2 in Carusone, Johns, Martin; "Analog Integrated Circuit Design", akademia.no or The Bandgap Reference - A Circuit for All Seasons
| What | Lib/Folder | Cell/Name |
|---|---|---|
| Schematic | design/RPLY_BIAS_SKY130NM | RPLY_BIAS |
| Layout | design/RPLY_BIAS_SKY130NM | RPLY_BIAS |
| Version | Status | Comment |
|---|---|---|
| 0.1.0 | ❌ | Make something |
| Signal | Direction | Domain | Description |
|---|---|---|---|
| VDD_1V8 | Input | VDD_1V8 | Main supply |
| VSS | Input | Ground | |
| PWRUP_1V8 | Input | VDD_1V8 | Power up the circuit |
| IBPS_1U[3:0] | Output | VDD_1V8 | PTAT bias current |
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Technology | Skywater 130 nm | |||
| VDD_1V8 | 1.7 | 1.8 | 1.9 | V |
| IBP_1U | ||||
| Temperature | -40 | 27 | 125 | C |
| Stage | TYPE | Status | Comment |
|---|---|---|---|
| Specification | DOC | ✅ | |
| Schematic | VIEW | ✅ | |
| Schematic simulation | VER | N/A | |
| Layout | VIEW | ❌ | |
| Layout parasitic extraction | VIEW | ❌ | |
| LPE simulation | VER | ❌ | |
| LVS | VER | ❌ | |
| DRC | VER | ❌ | |
| ERC | VER | ❌ | |
| ANT | VER | ❌ |