wsnyder

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

verilator_book

Notes on Verilator

Cores-SweRV

SweRV EH1 core

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

myhdl

The MyHDL development repository

conda-packages

Conda build recipes for the toolchains needed by LiteX / MiSoC firmware

ivtest

Regression test suite for Icarus Verilog. (OBSOLETE)

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

wbuart32

A simple, basic, formally verified UART controller

EasyCLA-code_only

sphinx-example

A mini-tutorial / cheatsheet / link-collection to get you started documenting Python code using Sphinx.

stylishsv-test

verilator

Verilator open-source SystemVerilog simulator and lint system

verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.