wisen's repositories
ai-edu
AI education materials for Chinese students, teachers and IT professionals.
arm-enterprise-acs
ARM Enterprise ACS
biriscv
32-bit Superscalar RISC-V CPU
cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
DDR
A simple DDR3 memory controller
docker_env
prepare some docker env build script for daily developements
DSP-RTL-Lib
RTL Verilog library for various DSP modules
dspfilters
A collection of demonstration digital filters
FPGA-DDR-SDRAM
An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
InteractiveHtmlBom
Interactive HTML BOM generation plugin for KiCad
interpolation
Digital Interpolation Techniques Applied to Digital Signal Processing
mptcp_net-next
Development version of the Upstream MultiPath TCP Linux kernel
NyuziProcessor
GPGPU microprocessor architecture
openISP
Image Signal Processor
riffa
The RIFFA development repository
rocket-chip
Rocket Chip Generator
Signal-Android
A private messenger for Android.
skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
spi-master
SPI Master for FPGA - VHDL and Verilog
ThinkDSP
Think DSP: Digital Signal Processing in Python, by Allen B. Downey.
uperf
Userspace performance controller for android
VirtualApp
Virtual Engine for Android(Support 12.0 in business version)
vivado-risc-v-experiment
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro