wallento

or1200mp

Multiprocessor variant of OpenRISC 1200 processor

board_armjtag_pmod_compatible

Connector board (ARM) JTAG, Pmod compatible

mooreandmore

Data to print Moore's law

pmod_switchbox

Pmod Switchbox

uart16550

Fork from OpenCores UART 16550

component-libraries

EDA component libraries

lowrisc-fpga

Untethered (stand-alone) FPGA implementation of the lowRISC SoC

lowrisc-untether

lowRISC: Untethered Rocket on KC705 (and other FPGA boards)

mgpio

Multi-bank General Purpose I/O

newlib

Newlib mirror

nexys4ddr

Open source and properly licensed code for the Digilent Nexys 4 DDR peripherals

or1ksim_reentrant

Reentrant version of the OpenRISC simulator

orpsoc-cores

Core description files for ORPSoCv3

verilog-lib

Fine selection of small Verilog modules under MIT license

wb_interconnect

Wishbone Interconnect Modules

ArchC

Mirror of the ArchC Source Code

arm-trusted-firmware

ARM Trusted Firmware

glip

Generic Logic Interfacing Project

mad-workshop.de

MAD Workshop Website

openrisc-landing

Draft for OpenRISC landing page

optee_os

Trusted side of the TEE

or1k-ci-tests

OR1K Continuous Integration tests

or1k-gcc

or1k-src

OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)

or1ksim

The OpenRISC 1000 architectural simulator