vvvvain's repositories
retraining-free-quantization
RFQuant: Retraining-free Model Quantization via One-Shot Weight-Coupling Learning, CVPR (2024)
fpgaconvnet-model
Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
training-mixed-precision-quantized-networks
This repository containts the pytorch scripts to train mixed-precision networks for microcontroller deployment, based on the memory contraints of the target device.
lsq-net
Unofficial implementation of LSQ-Net, a neural network quantization framework
MTFNN-CO
[IEEE TMC 2020] "Computation Offloading in Multi-Access Edge Computing: A Multi-Task Learning Approach" and [IEEE GlobeCom 2023] "A Multi-Head Ensemble Multi-Task Learning Approach for Dynamical Computation Offloading" by TensorFlow
cnn_hardware_acclerator_for_fpga
This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
AcceLeNetor
FYP project. A VerilogHDL based hardware accelerator.
nano-BERT
Nano-BERT is a straightforward, lightweight and comprehensible custom implementation of BERT, inspired by the foundational "Attention is All You Need" paper. The primary objective of this project is to distill the essence of transformers by simplifying the complexities and unnecessary details.
opencl-hls-cnn-accelerator
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
CNN-hw-accelerator
CNN hardware accelerator to accelerate quantized LeNet-5 model
SpringBoot_Web
首次尝试使用Git直接将IDEA项目上传至Github
JavaPractice
尝试使用Git将IDEA项目上传
My-Java-Study
尝试入门面向对象** & Java
Hello-World
尝试学习使用Github的第一步。
bert-on-silicon
Research and Materials on Hardware implementation of BERT (Bidirectional Encoder Representations from Transformers) Model
Active-Client-Selection-for-Communication-efficient-Federated-Learning
Active Client Selection for Federated Learning
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
udp_rmii_100MHz
Implement 100 MHz Ethernet in Verilog, including ARP and UDP, support UDP fragments
BRAM_DDR3_HDMI
在FPGA中将图像数据输入到DDR3中，再输送到HDMI接口上进行显示。
BlockConv
[TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA
trans-fat
An FPGA Accelerator for Transformer Inference