This is the FPGA implementation of PIEO scheduler. The design was synthesized on an Altera Stratix V FPGA. For more information, please refer to our SIGCOMM'19 paper.
A Fast, Scalable and Programmable Packet Scheduler in Hardware
This is the FPGA implementation of PIEO scheduler. The design was synthesized on an Altera Stratix V FPGA. For more information, please refer to our SIGCOMM'19 paper.
A Fast, Scalable and Programmable Packet Scheduler in Hardware