Beast code in Giters

Vishal Shrivastav's repositories

A Fast, Scalable and Programmable Packet Scheduler in Hardware

Language:SystemVerilog3300

Stateful Multi-Pipelined Programmable Switches

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Programmable Multi-Dimensional Table Filters for Line Rate Network Functions

Language:SystemVerilog400

NDP datacenter stack

Language:Mathematica100

Language:Python100

Yet Another Packet Simulator (YAPS)

Language:C++BSD-3-Clause100

Connectal is a framework for software-driven hardware development.

Language:BluespecMIT000

Language:Bluespec000

Generates Makefiles to synthesize, place, and route verilog using Vivado

Language:Tcl000

ns-2.35 patched with ExpressPass

Language:C++000

Language:Bluespec000