vegaluisjose

mlx-rag

Explore a simple example of utilizing MLX for RAG application running locally on your Apple Silicon device.

reticle

vast

Verilog AST

reticle-evaluation

Reticle evaluation (PLDI 2021)

primitives

vta-next

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

blob

bollard

Docker daemon API in Rust

calyx

Intermediate Language (IL) for Hardware Accelerator Generators

demo

edifier

Like an emulsifier, edifier aims to allow you to mix rust and edif.

figures

fprof

HLS-Tiny-Tutorials

This is forked from Xilinx/HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL

octoai-logo-gif

Creates a foody logo GIF

pre-eval

PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.

rdevice

react-gh-pages

reticle-regress

reticle-testing

rust-pickle

rust-playground

sabana_sha_test

Sabana SHA accelerator integration example

test-cd

tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

tvm-demo

tvm-vta

Open, Modular, Deep Learning Accelerator

vegaluisjose.github.io