ueeeehy

SQL2FPGA

[FCCM'23] SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms

spdk

Storage Performance Development Kit

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

LeFlow

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

oh

Verilog library for ASIC and FPGA designers

xls

XLS: Accelerated HW Synthesis

hdl

HDL libraries and projects

e203_hbirdv2

The Ultra-Low Power RISC-V Core

chisel

Chisel: A Modern Hardware Design Language

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

RTLFixer

Fix syntax errors of LLM-generated RTL

matchlib

SystemC/C++ library of commonly-used hardware functions and components for HLS.

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

llm.c

LLM training in simple, raw C/CUDA

opi

OPI Main Repository

FPGA_as_a_Service

dma_ip_drivers

Xilinx QDMA IP Drivers

Vitis-In-Depth-Tutorial

XRT

Run Time for AIE and FPGA based platforms

Vitis-HLS-Introductory-Examples

HLS

Vitis HLS LLVM source code and examples

Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

Vitis_Accel_Examples

Vitis_Accel_Examples

Vitis-Tutorials

Vitis In-Depth Tutorials

Vitis_Libraries

Vitis Libraries

Riscy-SoC

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog