tsengs0's repositories
ECC_Hardware
Hardware implementation of Error-Correction Code in Verilog
IB_layerLDPC_asymAccess_memShare
Enhancement of InformationBottleneck Implementation on FPGAs
riscv-decoder
Python-based RISC-V decoder and verifier
SingleCycleMIPS_Processor
Implementation of simple single-cycle MIPS ISA with branch instructions for subroutine
CMOS_Standard_Cell_Library
CMOS standard cell library (schematic and layout) using Electric VLSI and SPICE sim, Spring 18
Generic_SRAM_APB
RTL design of a generic SRAM module with APB I/F.
Intra-task-DVFS-simulator
A cycle-accurate simulator for hard real-time system for my master thesis. It perform Intra-task DVFS behaviour within execution of periodic tasks aiming at reducing response time jitter and energy consumption.
MulticoreCache_sim
A simple simulator for evaluating the hit/miss ratio of L1 data cache under multicore system with one main memory.
QC_LDPC_Construction_Optimisation
A framework of constructing Quasi-Cyclic LDPC Codes using some optimisation approaches.
RISC-V-Project
This is a simple exercise of implementing microprocessor based on RISC-V instruction set.
SystemC_Exercise
Those are execrise programs whilst I learnt the SystemC (systemc.2.3.2)
UART_RTL_UVM
This is a simple exercise of UART transceiver's RTL design along with UVM-based verification
common_cells
Common SV components
CTS_Paper_Reproduction
reproduction paper research in low voltage clock tree design
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
DRAM_AdaptiveRefresh
A proposal of new adaptive refresh mechanism and its verification
dvb_fpga
RTL implementation of components for DVB-S2
ece5745-tut5-asic-tools
ECE 5745 Tutorial 5: Synopsys/Cadence ASIC Tools
esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
InformationBottleneck_RTL_Generator
A HDL code generator to construct the Information Bottleneck based LDPC decoder architecture on FPGAs
Learning_AnalogIC
This repository is to keep the record of all my learning of analogue circuit.
LTspice-Basics
A set of simulation exercises to get you up and running with LTspice
ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
riscv_reference
RISC-V CPU Core (RV32IM)
RTL_design_of_system_bus_interface
This is my exercise projects of RTL implementation of various system bus slaver and master I/F, e.g. APB, AHB and AXI.
SimpleSDRAM_Controller-
Implementatoin of a simple SDRAM controller for target platform of DE1-SoC
tbengy
Python Tool for UVM Testbench Generation