tsengs0

tsengs0

Geek Repo

Company:JAIST

Location:Japan & Taiwan

Github PK Tool:Github PK Tool

tsengs0's repositories

ECC_Hardware

Hardware implementation of Error-Correction Code in Verilog

Language:VerilogStargazers:6Issues:2Issues:0

IB_layerLDPC_asymAccess_memShare

Enhancement of InformationBottleneck Implementation on FPGAs

Language:VerilogStargazers:1Issues:0Issues:0

riscv-decoder

Python-based RISC-V decoder and verifier

Language:PythonStargazers:1Issues:0Issues:0

SingleCycleMIPS_Processor

Implementation of simple single-cycle MIPS ISA with branch instructions for subroutine

Language:VHDLStargazers:1Issues:1Issues:0

cache-sim

cache simulator

Language:C++License:MITStargazers:0Issues:1Issues:0
Language:C++Stargazers:0Issues:2Issues:0

CMOS_Standard_Cell_Library

CMOS standard cell library (schematic and layout) using Electric VLSI and SPICE sim, Spring 18

Language:AGS ScriptStargazers:0Issues:2Issues:0

Generic_SRAM_APB

RTL design of a generic SRAM module with APB I/F.

Language:SystemVerilogLicense:MITStargazers:0Issues:0Issues:0

Intra-task-DVFS-simulator

A cycle-accurate simulator for hard real-time system for my master thesis. It perform Intra-task DVFS behaviour within execution of periodic tasks aiming at reducing response time jitter and energy consumption.

Language:C++License:GPL-3.0Stargazers:0Issues:2Issues:0

MulticoreCache_sim

A simple simulator for evaluating the hit/miss ratio of L1 data cache under multicore system with one main memory.

Language:C++Stargazers:0Issues:2Issues:0

QC_LDPC_Construction_Optimisation

A framework of constructing Quasi-Cyclic LDPC Codes using some optimisation approaches.

Language:C++Stargazers:0Issues:0Issues:0

RISC-V-Project

This is a simple exercise of implementing microprocessor based on RISC-V instruction set.

Language:VerilogStargazers:0Issues:2Issues:0

SystemC_Exercise

Those are execrise programs whilst I learnt the SystemC (systemc.2.3.2)

Language:C++Stargazers:0Issues:2Issues:0

UART_RTL_UVM

This is a simple exercise of UART transceiver's RTL design along with UVM-based verification

Language:SystemVerilogStargazers:0Issues:0Issues:0

common_cells

Common SV components

License:NOASSERTIONStargazers:0Issues:0Issues:0

CTS_Paper_Reproduction

reproduction paper research in low voltage clock tree design

Language:PerlStargazers:0Issues:0Issues:0

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

License:NOASSERTIONStargazers:0Issues:0Issues:0

DRAM_AdaptiveRefresh

A proposal of new adaptive refresh mechanism and its verification

Language:C++Stargazers:0Issues:1Issues:0

dvb_fpga

RTL implementation of components for DVB-S2

License:GPL-3.0Stargazers:0Issues:0Issues:0

ece5745-tut5-asic-tools

ECE 5745 Tutorial 5: Synopsys/Cadence ASIC Tools

Stargazers:0Issues:0Issues:0

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

License:NOASSERTIONStargazers:0Issues:0Issues:0

InformationBottleneck_RTL_Generator

A HDL code generator to construct the Information Bottleneck based LDPC decoder architecture on FPGAs

Language:VHDLStargazers:0Issues:0Issues:0

Learning_AnalogIC

This repository is to keep the record of all my learning of analogue circuit.

Language:AGS ScriptStargazers:0Issues:0Issues:0

LTspice-Basics

A set of simulation exercises to get you up and running with LTspice

Language:AGS ScriptLicense:MITStargazers:0Issues:0Issues:0

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

License:MITStargazers:0Issues:0Issues:0
Language:C++Stargazers:0Issues:1Issues:0

riscv_reference

RISC-V CPU Core (RV32IM)

Language:VerilogLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

RTL_design_of_system_bus_interface

This is my exercise projects of RTL implementation of various system bus slaver and master I/F, e.g. APB, AHB and AXI.

Language:VerilogStargazers:0Issues:0Issues:0

SimpleSDRAM_Controller-

Implementatoin of a simple SDRAM controller for target platform of DE1-SoC

Language:VerilogStargazers:0Issues:0Issues:0

tbengy

Python Tool for UVM Testbench Generation

Language:PythonLicense:MITStargazers:0Issues:0Issues:0