thesourcerer8 / SoC_Automation

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SoCGen

A truly no man in the loop.

This program automates SoC design through taking JSON input and generating verilog HDL for the SoC. We're working on the integration with OpenLane to generate the final GDS2.
Currently we support AMBA AHB for the high-speed (main) bus and APB for the low speed peripherals bus.

Getting Started

This instruction will get you a copy of the project up and running on your local machine for development and testing purposes.

git clone https://github.com/habibagamal/SoC_automation

If you need help with how to run the program

node ./src/sys_gen.js -help 

To generate the full SoC .v files

node ./src/sys_gen.js -soc <soc.json> -mastersLib <masters_lib.json> -IPlib <ip_lib.json> -subsystem <subsystem.json> -outDir <output directory> 
  • Omit any fields you don't need in the above command.
  • If there are no subsystems or real masters, you can ommit "-subsystem <subsystem.json>" or "-mastersLib <masters_lib.json>", respectively, from the command.

Expected input

For instructions on how to write the JSON file for:

Directory structure

  • systems: contains soc examples
  • IPs: contains JSON for IPs library and verilog files for open-source IPs
  • masters: contains JSON for masters library and master-related files
  • src: contains source code
  • JSON_format_doc: contains documentation for JSON format
  • Images: contains images used in README

Memory Address Sketch

For AHB

For APB

Currently supported features

  • Having multiple masters (tested on dummy masters)
  • Having multiple buses
  • Using created and open source verification IPs for testing
  • Using IPs that are not APB or AHB compatible
  • Auto-generating self-checking testbench

Flow

System Block Diagram

This diagram represents this example

Go here to download Arm Cortex M0, M3 files
Check this poster and video presented in DAC 2020 Young Fellowship Program about the project

Used Projects

  • Arbiter taken from here

To-do

  • Datasheet generation
  • Hardening using openLane

Authors

About

License:GNU General Public License v2.0


Languages

Language:Verilog 76.4%Language:JavaScript 17.1%Language:C 4.0%Language:Assembly 2.3%Language:Makefile 0.2%Language:Shell 0.1%