Sumeet Kumar Sahoo (sumu007)

sumu007

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Company:Hexaware Technologies

Location:India

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Sumeet Kumar Sahoo's repositories

Pandas-Pathway

It consists of basics data manipulation using pandas

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aws-ml-guide

[Video]AWS Certified Machine Learning-Specialty (ML-S) Guide

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8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

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awesome-competitive-programming

:gem: A curated list of awesome Competitive Programming, Algorithm and Data Structure resources

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Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

License:Apache-2.0Stargazers:0Issues:0Issues:0

Leetcode_company_frequency

Collection of leetcode company tag problems. Periodically updating.

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Voice-Based-Motor-Control

A verilog HDL based project to control a servomotor with voice commands from an android phone.

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minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

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SPOJ

SPOJ solutions (user: mahmud2690)

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FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

License:MITStargazers:0Issues:0Issues:0

Building-A-Processor---Project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

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Computer-Engineering-Projects

Digital computer structure, Hardware Design Lab & Introduction to Computers for computer engineering projects in C, C#, Assembly, Pspice.

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FPGA

BUAA Computer Organization Project8 FPGA

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Computer-Organization-and-Architecture-LAB

Solution to COA LAB Assgn, IIT Kharagpur

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course-aws

Notes & exercises for Coursera AWS course

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Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

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Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

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VerilogTutorial

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

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udacity-Intro-to-Machine-Learning

My solutions to quizzes, exercises, and projects in the Udacity Intro to Machine Learning course

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huffman

Using huffman coding to compress-decompress real-world files

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Interrupt_Controller

An 8 input interrupt controller written in Verilog.

License:GPL-3.0Stargazers:0Issues:0Issues:0