sifferman / schematics

Examples of how to Generate Schematics from SystemVerilog Synthesis Tools

HDL to Schematic Examples

This collection showcases examples of generating schematics from SystemVerilog code using various synthesis tools such as Yosys, Vivado, Genus, and Design Compiler.

Synlig + Yosys + netlistsvg

1. Install the following:

   • https://github.com/nturley/netlistsvg
   • https://github.com/chipsalliance/synlig

cd yosys
make

Vivado

1. Download Vivado: https://www.xilinx.com/support/download.html

cd vivado
make

Genus

cd genus
make

Design Compiler

cd design_compiler
make