This repo provides examples of how to use multiplexers in IEEE 1800 SystemVerilog.
always_comb begin
if (a)
b = c;
else
b = d;
end
# OSS-CAD-Suite and Zachjs-sv2v
wget -O - https://raw.githubusercontent.com/sifferman/hdl-tool-installer/main/install | bash -s -- <build_dir> --oss-cad-suite --zachjs-sv2v
- netlistsvg: https://github.com/nturley/netlistsvg
- Vivado: https://www.xilinx.com/support/download.html
cd registerfile_example
make