葉舜良's starred repositories
SelfManagingDRAM
Source code for evaluating the performance and DRAM energy benefits of Self-Managing DRAM (SMD), proposed in https://arxiv.org/abs/2207.13358
DAMOV
DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)
ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
eth-computer-architecture
ETH Computer Architecture - Fall 2020
play_with_dramsim3
MEMORY CENTRIC SYSTEMS FOR AI(CSI6207-01) Lecture at Yonsei(20-1)
axi_mem_if
Simple single-port AXI memory interface
sdram-controller
Verilog SDRAM memory controller
FPGA_ThreeLevelStorage
【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
Cache-Controller
Two Level Cache Controller implementation in Verilog HDL
systemc-examples
A repository for SystemC Learning examples
processor_risc
A simple processor implemented in SystemC
ICLab-2023
Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)
Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
Hardware-Security
Hardware Security Labs