secworks

resume.github.com

Resumes generated using the GitHub informations

curl

A command line tool and library for transferring data with URL syntax, supporting DICT, FILE, FTP, FTPS, GOPHER, GOPHERS, HTTP, HTTPS, IMAP, IMAPS, LDAP, LDAPS, MQTT, POP3, POP3S, RTMP, RTMPS, RTSP, SCP, SFTP, SMB, SMBS, SMTP, SMTPS, TELNET, TFTP, WS and WSS. libcurl offers a myriad of powerful features

al-khaser

Public malware techniques used in the wild: Virtual Machine, Emulation, Debuggers, Sandbox detection.

verilator

Verilator open-source SystemVerilog simulator and lint system

CryptoGotchas

A collection of common (interesting) cryptographic mistakes and learning resources.

pqm4

Post-quantum crypto library for the ARM Cortex-M4

oscar64

Optimizing Small memory C Compiler Assembler and Runtime for C64

chipwhisperer-jupyter

Interactive ChipWhisperer tutorials using Jupyter notebooks.

synlig

SystemVerilog support for Yosys

tkey-ssh-agent

SSH Agent for TKey, the flexible open hardware/software USB security key 🔑

kaiju

CERT Kaiju is a binary analysis framework extension for the Ghidra software reverse engineering suite. This repository is a "mirror" -- please file tickets, bug reports, or pull requests at the upstream home in @CERTCC: https://github.com/certcc/kaiju

Caliptra

Caliptra IP and firmware for integrated Root of Trust block

ent_random_sequence_tester

Utility for testing random and pseudorandom sequences, either as bytes or bit streams, reporting entropy, mean value, serial correlation, chi square, and Monte Carlo estimate of an value, serial correlation, chi square, and Monte Carlo estimate of π.

aes-min

Minimal AES-128 encryption. Suitable for small embedded systems. Including an on-the-fly key schedule variant for minimal RAM usage.

vidbo

Virtual Development Board

drawio-hdl-builder

Drawio => VHDL and Verilog

FPGA_NTP_SERVER

A FPGA implementation of the NTP and NTS protocols

BrightAI-Blackwire

BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard

tkey-verification

Vendor signing and user verification of TKey genuineness

no2muacm

Drop In USB CDC ACM core for iCE40 FPGA

circuitpainter

Create PCBs using a simplfiied graphics language

age-plugin-tkey

age plugin for keeping keys with a TKey USB security key

ascon-verilog

Verilog Hardware Design of Ascon v1.2

Cryptum

Encrypted file storage powered by the Tillitis TKey

BlackwireSpinal

Blackwire SpinalHDL components implementing WireGuard primitives

femsmahus2

Fem små hus v2, also known as Robust Internet.

ent

A header-only library that applies various tests to sequences of bytes stored in files and reports the results of those tests. The class is useful for evaluating pseudorandom number generators for encryption and statistical sampling applications, compression algorithms, and other applications where the information density of a file is of interest.

Finka

Finka is the VexRiscv based SoC in Blackwire responsible for WireGuard session management

noekeon-verilog

riscv-opcodes

RISC-V Opcodes