secworks

sha1

Verilog implementation of the SHA-1 cryptgraphic hash function

sha512

Verilog implementation of the SHA-512 hash function.

siphash

Hardware implementation of the SipHash short-inout PRF

gift

Hardware implementation of the GIFT-128 lightweight block cipher

poly1305

Hardware implementation of the poly1305 message authentication function.

uart

A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.

cbc

CBC block cipher mode of operation for AES.

figaro

Implementation of the FiGaRO TRNG for FPGAs

md5

Hardware implementation of the hash function md5

aes_mask

Experimental core for performing masking of AES by generating noise.

curve25519

Verilog 2001 of the Curve25519 elliptic curve based function.

rc4

An experimental RC4 hardware implementation with one cycle/iteration performance.

grain128

Hardware implementation of the Grain128AEAD stream cipher

xtea

Verilog implementation of the xtea block cipher

ice40_ultraplus_examples

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

salsa20

Sals20 Stream Cipher core in Verilog

vga

vga

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

blabla

Implementation of the BlaBla version of the ChaCha stream cipher

ca_prng

Cellular Automata based PRNG

FPGA_NTP_SERVER

openc910

OpenXuantie - OpenC910 Core

qarma

Verilog implementation of the lightweight block cipher QARMA

advent_of_code_2020

Repo for playing AoC 2020

advent_of_code_2021

Repo for playing Advent of Code 2021.

Castor_and_Pollux

A Juno-inspired dual oscillator

ed25519-unsafe-libs

List of unsafe ed25519 signature libs

rand_ice

Random number generator in Lattice iCEstick

seaglass

A truly native Matrix client for macOS - written in Swift/Cocoa, with E2E encryption support

timer

A simple timer with prescaler written in Verilog