saramkhalaf's repositories
engr378
These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA
Language:Python000
Language:Verilog000
Language:VerilogMIT000