Robert Winkler (rw1nkler)

rw1nkler

Geek Repo

Company:@antmicro

Location:Wrocław, Poland

Home Page:https://rw1nkler.github.io/blog/

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Organizations
antmicro

Robert Winkler's repositories

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cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

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fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format

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genanki

A Python 3 library for generating Anki decks

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github-actions

Templates for GitHub Actions

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nvme-cli

NVMe management command line interface.

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prjxray

Documenting the Xilinx 7-series bit-stream format.

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python-symbiflow-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

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socketcluster-client-go

GO client for socketcluster

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sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

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symbiflow-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

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symbiflow-docs

Documentation for SymbiFlow

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symbiflow-examples

Example designs showing different ways to use SymbiFlow toolchains.

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vcd_parsealyze

A Value Change Dump (VCD) file parser and analyzer

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vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

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xls

XLS: Accelerated HW Synthesis

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yosys

Yosys Open SYnthesis Suite

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