Antmicro

kenning

raviewer

Raw image/video data analyzer

renode

Renode - virtual development tool for multinode embedded networks

verilator

Verilator open-source SystemVerilog simulator and lint system

dts2repl

kenning-pipeline-manager

ecp5-dc-scm

Experimental Lattice ECP5-driven Data Center Security Communication Module

hardware-components

tlib

verilator-verification-features-tests

protoplaster

topwrap

A Python package for generating HDL wrappers and top modules for HDL sources

rdfm

verible-indexer

antmicro-jetson-orin-baseboard-kernel-5-10

Cores-VeeR-EL2

VeeR EL2 Core

Surelog

System Verilog 2017 Pre-processor, Parser

uvm-verilator

f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

llvm-disas

slang

SystemVerilog compiler and language services

test-colabs

visual-system-designer-resources

axi-vip

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

designer-media-files

jswasi-rootfs

mender

Mender over-the-air software updater client.

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

UHDM

Universal Hardware Data Model