Rok Krajnc (rkrajnc)

rkrajnc

Geek Repo

Location:Slovenia

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Rok Krajnc's repositories

minimig-mist

Minimig for the MiST board

Language:VerilogLicense:GPL-3.0Stargazers:63Issues:22Issues:88

minimig-de1

Minimig for the DE1 board

Language:VerilogLicense:GPL-3.0Stargazers:47Issues:20Issues:3

mandelbrot_fpga

Mandelbrot set implemented on an FPGA

Language:VerilogLicense:GPL-3.0Stargazers:5Issues:3Issues:0

FpgaSnes

SNES FPGA Emulator

Language:CStargazers:3Issues:3Issues:0

Omega

Bare metal Amiga Emulator

Language:CLicense:MPL-2.0Stargazers:3Issues:2Issues:0

spi_mem_programmer

A simple verilog module for programming (Q)SPI flash memories.

Language:VerilogLicense:MITStargazers:2Issues:2Issues:0

915MHzEdisonExplorer

A 915MHz block for the Intel Edison.

Language:KiCadStargazers:1Issues:2Issues:0

cv32e40p

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

Language:SystemVerilogLicense:NOASSERTIONStargazers:1Issues:0Issues:0

dsp

Header only C++14 library containing various digital signal processing utilities.

Language:C++License:LGPL-3.0Stargazers:1Issues:3Issues:0

fx68k

FX68K 68000 cycle accurate SystemVerilog core

Language:SystemVerilogLicense:GPL-3.0Stargazers:1Issues:3Issues:0

fxpmath

A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.

Language:PythonLicense:MITStargazers:1Issues:2Issues:0
Language:SystemVerilogLicense:Apache-2.0Stargazers:1Issues:3Issues:0

mor1kx

mor1kx - an OpenRISC 1000 processor IP core

Language:VerilogLicense:NOASSERTIONStargazers:1Issues:1Issues:0

oh

Silicon proven Verilog library for IC and FPGA designers

Language:VerilogLicense:MITStargazers:1Issues:3Issues:0

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Language:SystemVerilogLicense:NOASSERTIONStargazers:1Issues:3Issues:0

skrach-synth

An FPGA synthesizer with MIDI support

Language:VHDLLicense:GPL-3.0Stargazers:1Issues:2Issues:0

SPIFlashController

An FPGA SPI flash controller that presents a simple to use FIFO interface to the user.

Language:VerilogLicense:MITStargazers:1Issues:0Issues:0

adv_debug_sys

Advanced Debug System

Stargazers:0Issues:0Issues:0

aoc

Advent of Code https://adventofcode.com/

Language:PythonStargazers:0Issues:2Issues:0

conky

Simple Conky configuration for my desktop PC

Stargazers:0Issues:2Issues:0

dcpu16-asm-c

An assembler for DCPU-16, written in C.

Language:CStargazers:0Issues:3Issues:0

hdr-plus

HDR+ Implementation

Language:CLicense:MITStargazers:0Issues:2Issues:0

ibex-demo-system

A demo system for Ibex including debug support and some peripherals

Language:CLicense:Apache-2.0Stargazers:0Issues:1Issues:0

libsigrok

Read-only mirror of the official repo at git://sigrok.org/libsigrok. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

Language:CLicense:GPL-3.0Stargazers:0Issues:1Issues:0

minimig-common

Common minimig codebase, usable for different platforms

Stargazers:0Issues:3Issues:0

openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

plasma-simpleMonitor

plasma-simpleMonitor

Language:QMLLicense:GPL-3.0Stargazers:0Issues:3Issues:0

SimpleDevice

Device skeleton in C using bebbos gcc6

Language:CStargazers:0Issues:3Issues:0

Twist

Twist - node-based audio synthesizer

Language:CStargazers:0Issues:0Issues:0