riscv-steel / riscv-steel

Free collection of hardware modules written in Verilog for FPGAs and embedded systems.

https://riscv-steel.github.io/riscv-steel/

riscv-steel/riscv-steel Issues

Add GPIO unit to the SoC IP
Closed 2 months ago
Add SPI interface to the SoC IP
Closed 4 months ago
Byte order of instructions and data when accessing memory
Closed 6 months ago4
Using clog2
Closed 6 months ago3
The file name must match the module name
Closed 6 months ago2
Test compilation instructions
Closed a year ago2
Documentation page shows 404
Closed a year ago8
True TRAP_TAKEN in the EX stage causes record to be skipped without retry after TRAP
Closed 2 years ago5
Vector mode (mtvec)
Closed 2 years ago1
Synthesize on Zedboard
Closed 3 years ago5
FPGA board support
Closed 3 years ago3