RISC-V Non-ISA Specifications's repositories
riscv-asm-manual
RISC-V Assembly Programmer's Manual
riscv-elf-psabi-doc
A RISC-V ELF psABI Document
riscv-sbi-doc
Documentation for the RISC-V Supervisor Binary Interface
riscv-trace-spec
RISC-V Processor Trace Specification
riscv-toolchain-conventions
Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
riscv-iommu
RISC-V IOMMU Specification
riscv-c-api-doc
Documentation of the RISC-V C API
riscv-ap-tee
This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
riscv-device-tree-doc
RISC-V Specific Device Tree Documentation
tg-nexus-trace
RISC-V Nexus Trace TG documentation and reference code
riscv-brs
The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.
riscv-security-model
RISC-V Security Model
server-soc
The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
riscv-ap-tee-io
This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.
riscv-external-debug-security
The RISC-V External Debug Security Specification
riscv-server-platform
The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.
iopmp-spec
This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
riscv-ras-eri
The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.
e-trace-encap
E-Trace Encapsulation Specification
riscv-acpi-ffh
The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification
riscv-cbqri
This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.
server-soc-ts
Test suite for Server SoC
riscv-acpi-rimt
RISC-V ACPI I/O Mapping Table Specification
riscv-rpmi
RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control
riscv-iommu-invalidation
IOMMU Address Translation Cache Invalidation Commands Extensions
riscv-rqsc
Specification Documentation Repository for the RQSC RISC-V Quality of Services Controllers Table definition