Internal bus protocol error

[Taichi Ishitani]

Internal bus protocol error raised when a write access arrives during a read access is in progress.

To fix this error, the adapter module needs to hold which channel is active during an access in progress.
This could cause #121.

[Taichi Ishitani]

This is a test sequence to reproduce this error.

class ral_issue_121_test_sequence extends ral_test_sequence #(ral_hw_reset_test_sequence);
  task body();
    uvm_status_e    status[2];
    uvm_reg_data_t  read_data[2];

    for (int i = 0;i < 3;++i) begin
      p_sequencer.model.register_14.register_file_0.register_1.write(status[1], 32'hcafe_0000 | 32'(i));
      if (i inside {0, 2}) begin
        fork
          p_sequencer.model.register_14.register_file_0.register_1.read(status[1], read_data[1]);
        join_none
        #1;
        fork
          p_sequencer.model.register_14.register_file_0.register_0.write(status[0], 32'hdead_0000 | 32'(i));
        join_none
      end
      else begin
        fork
          p_sequencer.model.register_14.register_file_0.register_0.write(status[0], 32'hdead_0000 | 32'(i));
        join_none
        #1;
        fork
          p_sequencer.model.register_14.register_file_0.register_1.read(status[1], read_data[1]);
        join_none
      end
      wait fork;
      p_sequencer.model.register_14.register_file_0.register_0.read(status[0], read_data[0]);
    end
  endtask

  `tue_object_default_constructor(ral_issue_121_test_sequence)
  `uvm_object_utils(ral_issue_121_test_sequence)
endclass