No driver warning

[Taichi Ishitani]

Some signals between register and bit field modules have no driver for ease of RTL generation.
Synthesis tool may report this as warning and it's very noisy.

Warning: In design 'block_0', net 'g_register_13.w_bit_field_value[1]' has no drivers.  Logic 0 assumed. (LINT-3)
Warning: In design 'block_0', net 'g_register_13.w_bit_field_value[2]' has no drivers.  Logic 0 assumed. (LINT-3)
Warning: In design 'block_0', net 'g_register_13.w_bit_field_value[3]' has no drivers.  Logic 0 assumed. (LINT-3)
Warning: In design 'block_0', net 'g_register_13.w_bit_field_value[4]' has no drivers.  Logic 0 assumed. (LINT-3)

Therefore, these warnings should be cleared.

[Taichi Ishitani]

For SV/Verilog, use following macro:

`ifndef rggen_tie_off_unsed_signal
  `define rggen_tie_off_unsed_signal(WIDTH, VALID_BITS, RIF) \
  if (1) begin : g__tie_off \
    genvar __i; \
    for (__i = 0;__i < WIDTH;++__i) begin : g \
      if (!((VALID_BITS >> __i) & 1'b1)) begin : g \
        assign  RIF.read_data[__i]  = 1'b0; \
        assign  RIF.value[__i]      = 1'b0; \
      end \
    end \
  end
`endif

For VHDL, insert following code snippet.

\g_tie_off\: for \__i\ in 0 to 31 generate
  g: if (bit_slice(x"00000303", \__i\) = '0') generate
      bit_field_read_data(\__i\) <= '0';
      bit_field_value(\__i\) <= '0';
  end generate;
end generate;