-
25.88% 243085um 7918 cells 544 dff, 23.26 min gds, 13.55 viewer <- 384 synapses (16) x 16 x 8
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40.98% 393467um 12384 cells 800 dff, 19.59 min gds, <- 640 synapses (16) x 16 x 16 x 8
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43.67% 432050um 12932 cells 928 dff, 29.0 min gds, 47.26 viewer <- 640 synapses (16) x 16 x 16 x 8 fixed the weights
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45.23% 427921um 13795 cells 928 dff, 26.5 min gds <- 640 synapses (16) x 16 x 16 x 8 BN added
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17.09% 100777um 5116 cells 808 dff, 15.19 min gds <- 320 synapses (16) x 16 x 16 x 8 50% sparsity!
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24.72% 183035um 7957 cells 968 dff, 13.22 min gds <- 320 synapses (16) x 16 x 16 x 8 BN scale per neuron, 50% sparsity!
- 49.81%, 185466um 7977 cells 968 dff, 15.45 min gds <- 320 synapses (16) x 16 x 16 x 8 BN scale per neuron, 50% sparsity!
- 59.47%, 233359um 9486 cells 1128dff, 16.30 min gds <- 320 synapses (16) x 16 x 16 x 8 BN scale+add per neuron, 50% sparsity!
- 62.84%, 213588um 9624 cells 1142dff, 15.42 min gds <- 320 synapses (16) x 16 x 16 x 8 threshollds per layer, BN per neuron, 50% sparsity!
TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.
To learn more and get started, visit https://tinytapeout.com.
Edit the info.yaml and uncomment the source_files and top_module properties, and change the value of language to "Verilog". Add your Verilog files to the src folder, and list them in the source_files property.
The GitHub action will automatically build the ASIC files using OpenLane.
Please see the instructions for:
- Submit your design to the next shuttle on the website. The closing date is November 4th.
- Edit this README and explain your design, how it works, and how to test it.
- Share your GDS on your social network of choice, tagging it #tinytapeout and linking Matt's profile:
- LinkedIn #tinytapeout matt-venn
- Mastodon #tinytapeout @matthewvenn
- Twitter #tinytapeout @matthewvenn