MAESTRO is a cost-benefit model to evaluate dataflows over a general accelerator architecture. It receives dataflow and architecture description and provides buffer access counts, which can be integrated with energy models to produce energy consumption, roofline performance, which is throughput with full compute unit utilization, buffer size requirement, network-on-chip bandwidth requirement, and so on. We are currently validating the model. Until it finishes, we only distribute binary executables. For usages, please see our tutorial slides.
We are using the convention described in the image above. (C/K: Input/Output channel, Y/X: Input Row/Column, and R/S: Weight Row/Column)
In layerDecription directories, you will see example layer description files. The file contents look like the example above (vgg16_conv1.m).