Fast RISC-V Sail emulation using PyPy/RPython's JIT compiler
This repository contains Pydrofoil, an experimental emulator for RISC-V based on the Sail RISC-V ISA model. It achieves fast performance by doing dynamic binary translation (aka just-in-time compilation) from RISC-V guest instructions into host machine instructions. It's built on top of the RPython meta-jit compiler and reuses all its optimizations, backends, etc.
See https://docs.pydrofoil.org for the complete documentation